This invention relates generally to floating-point arithmetic units, and, more particularly, to IEEE 754 compliant asynchronous floating-point arithmetic units.
Efficient floating-point computation is important for a wide range of applications in science and engineering. Using computational techniques for conducting both theoretical and experimental research has become ubiquitous, and there is an insatiable demand for higher and higher performing VLSI systems. Today, this performance is limited by power constraints. The Top 500 supercomputer ranking now includes the energy-efficiency of the system as well as its performance. At the other end of the spectrum, embedded systems that have traditionally been considered low performance are demanding higher and higher throughput for the same power budget. Hence it is important to develop energy-efficient floating point hardware, not simply high performance floating-point hardware.
The IEEE 754 standard for binary floating-point arithmetic provides a precise specification of a floating-point adder (FPA). This specification was determined after much debate, and it took several years before hardware vendors developed IEEE-compliant hardware. Part of the challenge was the belief that: (i) implementing most of the standard was sufficient; (ii) ignoring a few infrequently occurring cases led to more efficient hardware. Unfortunately ignoring certain aspects of the standard can lead to unexpected consequences in the context of numerical algorithms. Today, most floating point hardware is IEEE-compliant or has an IEEE-compliant mode.
Therefore, there is a need to provide energy efficient IEEE 754 compliant floating-point arithmetic units.